3D7303 doc #96001 data delay devices, inc. 1 12/2/96 3 mt. prospect ave. clifton, nj 07013 monolithic triple fixed delay line (series 3D7303) features all-silicon, low-power cmos technology ttl/cmos compatible inputs and outputs vapor phase, ir and wave solderable auto- insertable (dip pkg.) low ground bounce noise leading- and trailing-edge accuracy delay range: 10 through 500ns delay tolerance: 2% or 1.0ns temperature stability: 3% typical (0c-70c) vdd stability: 1% typical (4.75v-5.25v) minimum input pulse width: 20% of total delay 14-pin dip available as drop-in replacement for hybrid delay lines functional description the 3D7303 triple delay line product family consists of fixed-delay cmos integrated circuits. each package contains three matched, independent delay lines. delay values can range from 10ns through 500ns. the input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. the 3D7303 is ttl- and cmos-compatible, capable of driving ten 74ls-type loads, and features both rising- and falling-edge accuracy. the all-cmos 3D7303 integrated circuit has been designed as a reliable, economic alternative to hybrid ttl fixed delay lines. it is offered in a standard 8-pin auto- insertable dip and a space saving surface mount 8-pin soic. data delay devices, inc. 3 packages 8 7 6 5 1 2 3 4 i1 i2 i3 gnd vdd o1 o2 o3 3D7303m dip 3D7303h gull-wing (300 mil) 1 2 3 4 8 7 6 5 i1 i2 i3 gnd vdd o1 o2 o3 3D7303z soic (150 mil) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 i1 n/c i2 n/c i3 n/c gnd vdd n/c o1 n/c o2 n/c o3 3D7303 dip 3D7303g gull-wing 3D7303k unused pins removed (300 mil) pin descriptions i1 delay line 1 input i2 delay line 2 input i3 delay line 3 input o1 delay line 1 output o2 delay line 2 output o3 delay line 3 output vcc +5 volts gnd ground n/c no connection table 1: part number specifications part number delay input restrictions dip-8 3D7303m 3D7303h soic-8 3D7303z dip-14 3D7303 3D7303g dip-14 3D7303k per line ( ns) max operating frequency absolute max oper. freq. min operating pulse width absolute min oper. p.w. -10 -10 -10 -10 10 1.0 33.3 mhz 100.0 mhz 15.0 ns 5.0 ns -15 -15 -15 -15 15 1.0 22.2 mhz 100.0 mhz 22.5 ns 5.0 ns -20 -20 -20 -20 20 1.0 16.7 mhz 100.0 mhz 30.0 ns 5.0 ns -25 -25 -25 -25 25 1.0 13.3 mhz 83.3 mhz 37.5 ns 6.0 ns -30 -30 -30 -30 30 1.0 11.1 mhz 71.4 mhz 45.0 ns 7.0 ns -40 -40 -40 -40 40 1.0 8.33 mhz 62.5 mhz 60.0 ns 8.0 ns -50 -50 -50 -50 50 1.0 6.67 mhz 50.0 mhz 75.0 ns 10.0 ns -100 -100 -100 -100 100 2.0 3.33 mhz 25.0 mhz 150.0 ns 20.0 ns -200 -200 -200 -200 200 4.0 1.67 mhz 12.5 mhz 300.0 ns 40.0 ns -300 -300 -300 -300 300 6.0 1.11 mhz 8.33 mhz 450.0 ns 60.0 ns -400 -400 -400 -400 400 8.0 0.83 mhz 6.25 mhz 600.0 ns 80.0 ns -500 -500 -500 -500 500 10.0 0.67 mhz 5.00 mhz 750.0 ns 100.0 ns note: any delay between 10 and 500 ns not shown is also available. 1996 data delay devices
3D7303 doc #96001 data delay devices, inc. 2 12/2/96 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes operational description the 3D7303 triple delay line architecture is shown in figure 1. the individual delay lines are composed of a number of delay cells connected in series. each delay line produces at its output a replica of the signal present at its input, shifted in time. the delay lines are matched and share the same compensation signals, which minimizes line-to-line delay deviations over temperature and supply voltage variations. input signal characteristics the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a maximum and an absolute maximum operating input frequency and a minimum and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1 , determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. to guarantee the table 1 delay accuracy for input frequencies higher than the maximum operating frequency , the 3D7303 must be tested at the user operating frequency. therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. the programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. nevertheless, it is strongly recommended that the engineering staff at data delay devices be consulted. operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1 , determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. to guarantee the table 1 delay accuracy for input pulse width smaller than the minimum operating pulse width , the 3D7303 must be tested at the user operating pulse width. therefore, to facilitate production and device identification, the part number will include a o1 i1 delay line delay line delay line o2 i2 o3 i3 temp & vdd compensation vdd gnd figure 1: 3D7303 functional diagram
3D7303 doc #96001 data delay devices, inc. 3 12/2/96 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) custom reference designator identifying the intended frequency and duty cycle of operation. the programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. nevertheless, it is strongly recommended that the engineering staff at data delay devices be consulted. power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3D7303 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. the thermal coefficient is reduced to 600 ppm/c , which is equivalent to a variation , over the 0c-70c operating range, of 3% from the room-temperature delay settings and/or 1.0ns , whichever is greater. the power supply coefficient is reduced, over the 4.75v-5.25v operating range, to 1% of the delay settings at the nominal 5.0vdc power supply and/or 2.0ns , whichever is greater. it is essential that the power supply pin be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. device specifications table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v input pin current i in -1.0 1.0 ma 25c storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min max units notes static supply current* i dd 30 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 1 m a v ih = v dd low level input current i il 1 m a v il = 0v high level output current i oh -4.0 ma v dd = 4.75v v oh = 2.4v low level output current i ol 4.0 ma v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 ns c ld = 5 pf *i dd (dynamic) = 3 * c ld * v dd * f input capacitance = 10 pf typical where: c ld = average capacitance load/line ( pf) output load capacitance (c ld ) = 25 pf max f = input frequency ( ghz)
3D7303 doc #96001 data delay devices, inc. 4 12/2/96 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k w 10% supply voltage ( vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. 10k w 470 w 5pf device under test digital scope out1 out2 out3 out trig in ref trig figure 2: test setup device under test (dut) digital scope/ time interval counter pulse generator computer system printer in3 in2 in1 figure 3: timing diagram t plh t phl per in pw in t rise t fall 0.6v 0.6v 1.5v 1.5v 2.4v 2.4v 1.5v 1.5v v ih v il v oh v ol input signal output signal
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